View LTC6803-1_5702552.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

ltc 6820 1 6820f typical a pplica t ion fea t ures descrip t ion isospi isolated communications interface the lt c ? 6820 provides bidirectional spi communications between two isolated devices through a single twisted- pair connection. each ltc6820 encodes logic states into signals that are transmitted across an isolation barrier to another ltc6820. the receiving ltc6820 decodes the transmission and drives the slave bus to the appropriate logic states. the isolation barrier can be bridged by a simple pulse transformer to achieve hundreds of volts of isolation. the ltc6820 drives differential signals using matched source and sink currents, eliminating the requirement for a transformer center tap and reducing emi. precision window comparators in the receiver detect the differential signals. the drive currents and the comparator thresholds are set by a simple external resistor divider, allowing the system to be optimized for required cable lengths and desired signal-to-noise performance. microcontroller to spi slave isolated interface data rate vs cable length a pplica t ions n 1mbps isolated spi data communications n simple galvanic isolation using standard t ransformers n bidirectional interface over a single t wisted pair n supports cable lengths up to 100 meters n very low emi susceptibility and emissions n configurable for high noise immunity or low power n engineered for iso26262 compliant systems n requires no software changes in most spi systems n ultralow, 2a idle current n automatic wake-up detection n operating temperature range: C40c to 125c n 2.7v to 5.5v power supply n interfaces to all logic from 1.7v to 5.5v n available in 16-lead qfn and msop packages n industrial networking n battery monitoring systems n remote sensors l, lt , lt c , lt m , linear technology and the linear logo are registered trademarks and isospi is a trademark of linear technology corporation. all other trademarks are the property of their respective owners. patents pending. ip 120 100 meters twisted pair ltc6820 mstr mosi miso sck cs im master c sdo sdi sck cs ip 120 6820 ta01a ltc6820 mstr mosi miso sck cs im remote slave ic sdi sdo sck cs cable length (meters) 1 0 data rate (mbps) 0.2 0.4 0.6 0.8 1.2 10 100 6820 ta01b 1.0 cat-5 assumed
ltc 6820 2 6820f p in c on f igura t ion a bsolu t e maxi m u m r a t ings input supply voltages (v dd and v dds ) to gnd ........... 6 v pin voltages sck , cs , en ............... C 0.3 v to v dds + 0.3 v (6 v max ) ibi as , slow , ip , im ..... C 0.3 v to v dd + 0.3 v (6 v max ) al l other pin voltages .............................. C 0.3 v to 6v maximum source / sink current ip , im ................................................................. 30 ma mosi , miso , sck , cs ........................................ 20 ma o perating temperature range ltc 6 820i ............................................. C 40 c to 85 c ltc 6 820h .......................................... C 40 c to 125 c (notes 1, 2, 3) 16 15 14 13 5 6 7 8 top view 17 ud package 16-lead (3mm 3mm) plastic qfn 9 10 11 12 4 3 2 1mosi miso sck cs slow mstr ip im en ibias icmp gnd v dds pol pha v dd t jmax = 150c, ja = 58.7c/w exposed pad (pin 17) pcb connection to gnd is optional 1 2 3 4 5 6 7 8 en mosi miso sck cs v dds pol pha 16 15 14 13 12 11 10 9 ibias icmp gnd slow mstr ip im v dd top view ms package 16-lead plastic msop t jmax = 150c, ja = 120c/w o r d er i n f or m a t ion lead free finish tape and reel part marking* package description specified temperature range ltc6820iud#pbf ltc6820iud#trpbf lgfm 16-lead (3mm 3mm) plastic qfn C40c to 85c ltc6820hud#pbf ltc6820hud#trpbf lgfm 16-lead (3mm 3mm) plastic qfn C40c to 125c ltc6820ims#pbf ltc6820ims#trpbf 6820 16-lead plastic msop C40c to 85c ltc6820hms#pbf ltc6820hms#trpbf 6820 16-lead plastic msop C40c to 125c consult lt c marketing for parts specified with wider operating temperature ranges. *the temperature grade is identified by a label on the shipping container. consult lt c marketing for information on nonstandard lead based finish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ specified temperature range ltc 6 820i ............................................. C 40 c to 85 c ltc 6 820h .......................................... C 40 c to 125 c storage temperature range .................. C 65 c to 150 c lead temperature ( soldering , 10 sec ) ms op ............................................................... 30 0 c
ltc 6820 3 6820f e lec t rical c harac t eris t ics the l denotes the specifications which apply over the full specified temperature range, otherwise specifications are at t a = 25c. v dd = 2.7v to 5.5v, v dds = 1.7v to 5.5v, r bias = 2k to 20k unless otherwise specified. all voltages are with respect to gnd. symbol parameter conditions min typ max units power supply v dd operating supply voltage range l 2.7 5.5 v v dds io supply voltage range (level shifting) affects cs, sck, mosi, miso and en pins l 1.7 5.5 v i dd supply current, ready/active states (note 4) r bias = 2k (i b = 1 ma ) 1/ t clk = 0 mhz 1/ t clk = 1 mhz l 4 4.8 7 5.8 ma ma r bias = 20k (i b = 0.1ma) 1/ t clk = 0 mhz 1/ t clk = 1 mhz l 1.3 2 2.4 2.9 ma ma supply current, idle state mstr = 0v mstr = v dd l l 2 1 6 3 a a i dds io supply current (note 5) spi inputs and en pin at 0v or v dds , spi outputs unloaded l 1 a biasing v bias voltage on ibias pin ready/active state idle state l 1.9 2.0 0 2.1 v v i b isolated interface bias current (note 6) r bias = 2k to 20k l v bias /r bias ma a ib isolated interface current gain v a 1.6v i b = 1ma i b = 0.1ma l l 18 18 20 20 22 24 ma/ma ma/ma v a transmitter pulse amplitude v a = |v ip C v im | v dd < 3.3v v dd 3.3v l l v dd C 1.7v 1.6 v v v icmp threshold-setting voltage on icmp pin v tcmp = a tcmp ? v icmp l 0.2 1.5 v i leak( icmp) leakage current on icmp pin v icmp = 0v to v dd l 1 a i leak( ip/ im) leakage current on ip and im pins idle state, v ip = v im = 0v to v dd l 2 a a tcmp receiver comparator threshold voltage gain v cm = v dd /2 to v dd C 0.2v, v icmp = 0.2v to 1.5v l 0.4 0.5 0.6 v/v v cm receiver common mode bias ip/im not driving (v dd C v icmp /3 C 167mv) v r in receiver input resistance single-ended to ip or im l 26 35 42 k idle/wake-up (see figures 13, 14, 15) v wake differential wake-up voltage (see figure 13) t dwell = 240ns l 240 mv t dwell dwell time at v wake v wake = 240mv l 240 ns t ready start-up time after wake detection l 8 s t idle idle time-out duration l 4 5.7 7.5 ms digital i/o v ih(cfg) digital voltage input high, configuration pins (pha, pol, mstr, slow) v dd = 2.7v to 5.5v (pol, pha, mstr, slow) l 0.7 ? v dd v v il(cfg) digital voltage input low, configuration pins (pha, pol, mstr, slow) v dd = 2.7v to 5.5v (pol, pha, mstr, slow) l 0.3 ? v dd v v ih(spi) digital voltage input high, spi pins (cs, sck, mosi, miso) v dds = 2.7v to 5.5v v dds = 1.7v to 2.7v l l 0.7 ? v dds 0.8 ? v dds v v v il(spi) digital voltage input low, spi pins (cs, sck, mosi, miso) v dds = 2.7v to 5.5v v dds = 1.7v to 2.7v l l 0.3 ? v dds 0.2 ? v dds v v v ih(en) digital voltage input high, en pin v dds = 2.7v to 5.5v v dds = 1.7v to 2.7v l l 2 0.85 ? v dds v v v il(en) digital voltage input low, en pin v dds = 2.7v to 5.5v v dds = 1.7v to 2.7v l l 0.8 0.25 ? v dds v v v oh digital voltage output high ( cs and sck) v dds = 3.3v, sourcing 2ma v dds = 1.7v, sourcing 1ma l l v dds C 0.2 v dds C 0.25 v v v ol digital voltage output low (mosi, miso, cs, sck) v dds = 3.3v, sinking 3.3ma v dds = 1.7v, sinking 1ma l l 0.2 0.2 v v
ltc 6820 4 6820f e lec t rical c harac t eris t ics the l denotes the specifications which apply over the full specified junction temperature range, otherwise specifications are at t a = 25c. v dd = 2.7v to 5.5v, v dds = 1.7v to 5.5v, r bias = 2k to 20k unless otherwise specified. all voltages are with respect to gnd. symbol parameter conditions min typ max units i leak(dig) digital pin input leakage current pha, pol, mstr, slow = 0v to v dd cs, sck, mosi, miso, en = 0v to v dds l 1 a c i/o input/output pin capacitance (note 9) 10 pf isolated pulse timing (see figure 2) t 1/2pw (cs) chip-select half-pulse width l 120 150 180 ns t inv(cs) chip-select pulse inversion delay l 200 ns t del(cs) chip-select response delay l 140 190 ns t ?pw (d) data half-pulse width l 40 50 60 ns t inv(d) data pulse inversion delay l 70 ns t del(d) data response delay (note 8) l 75 120 ns isospi? timingmaster (see figures 3, 4) t clk sck latching edge to sck latching edge (note 7) slow = 0 slow = 1 l l 1 5 s s t 1 mosi setup time before sck latching edge (note 8) l 25 ns t 2 mosi hold time after sck latching edge l 25 ns t 3 sck low t clk = t 3 + t 4 1s l 50 ns t 4 sck high t clk = t 3 + t 4 1s l 50 ns t 5 cs rising edge to cs falling edge l 0.6 s t 6 sck latching edge to cs rising edge (note 7) l 1 s t 7 cs falling edge to sck latch edge (note 7) l 1 s t 8 sck non-latch edge to miso valid (note 8) l 55 ns t 9 sck latching edge to short 1 transmit l 50 ns t 10 cs transition to long 1 transmit l 55 ns t 11 cs rising edge to miso rising (note 8) l 55 ns isospi timingslave (see figures 3, 4) t 12 isospi data recognized to sck latching edge (note 8) slow = 0 slow = 1 l l 110 0.9 145 1.1 185 1.4 ns s t 13 sck pulse width slow = 0 slow = 1 l l 90 0.9 115 1.1 150 1.4 ns s t 14 sck non-latch edge to isospi data transmit (note 8) slow = 0 slow = 1 l l 115 0.9 145 1.1 190 1.4 ns s t 15 cs falling edge to sck non-latch edge pha = 1 slow = 0 slow = 1 l l 90 0.9 120 1.1 160 1.4 ns s t 16 cs falling edge to isospi data transmit slow = 0 slow = 1 l l 200 1.8 265 2.2 345 2.8 ns s t 17 cs rising edge to sck latching edge pha = 1 slow = 0 slow = 1 l l 90 0.9 120 1.1 160 1.4 ns s t 18 cs rising edge to mosi rising edge l 35 ns t rtn data return delay slow = 0 slow = 1 l l 485 3.3 625 4 ns s note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: all currents into pins are positive, and all voltages are referenced to gnd unless other wise specified. note 3: the ltc6820i is guaranteed to meet specified performance from C40c to 85c. the ltc6820h is guaranteed to meet specified performance from C40c to 125c. note 4: active supply current (i dd ) is dependent on the amount of time that the output drivers are active on ip and im. during those times i dd will increase by the 20 ? i b drive current. for the maximum data rate 1mhz, the drivers are active approximately 10% of the time if mstr = 1, and 5%
ltc 6820 5 6820f typical p er f or m ance c harac t eris t ics supply current (idle) vs supply voltage supply current (idle) vs temperature supply current (ready/active) vs clock frequency supply current (ready) vs temperature input voltage threshold (except en pin) vs supply voltage (v dd or v dds ) e lec t rical c harac t eris t ics of the time if mstr = 0. see applications information section for more detailed information. note 5: the io supply pin, v dds , provides power for the spi inputs and outputs, including the en pin. if the inputs are near 0v or v dds (to avoid static current in input buffers) and the outputs are not sourcing current, then i dds includes only leakage current. note 6: the ltc6820 is guaranteed to meet specifications with r bias resistor values ranging from 2k to 20k, with 1% or better tolerance. those resistor values correspond to a typical i b that can range from 0.1ma (for 20k) to 1ma (for 2k). note 7: these timing specifications are dependent on the delay through the cable, and include allowances for 50ns of delay each direction. 50ns corresponds to 10m of cat -5 cable (which has a velocity of propagation of 66% the speed of light). use of longer cables would require derating these specs by the amount of additional delay. note 8: these specifications do not include rise or fall time. while fall time (typically 5ns due to the internal pull-down transistor) is not a concern, rising-edge transition time t rise is dependent on the pull-up resistance and load capacitance. in particular, t 12 and t 14 require t rise < 110ns (if slow = 0) for the slaves setup and hold times. therefore, the recommended time constant is 50ns or less. for example, if the total capacitance on the data pin is 25pf (including self capacitance c i/o of 10pf), the required pull-up resistor value is r pu 2k. if these requirements cant be met, use slow = 1. note 9: guaranteed by design. not tested in production. v dd = v dds , unless otherwise noted. frequency (khz) 0 1 supply current (ma) 2 3 4 5 6 7 200 400 600 800 6820 g01 1000 v dd = 5v, i b = 1ma v dd = 5v, i b = 0.1ma v dd = 3v, i b = 1ma v dd = 3v, i b = 0.1ma mstr = 1 temperature (c) ?50 ?25 4.8 supply current (ma) 5.0 5.3 0 50 75 6820 g02 4.9 5.2 5.1 25 100 125 v dd = 5v v dd = 3v i b = 1ma supply voltage (v) 1.5 2.5 0 input voltage threshold (v) 0.5 1.0 1.5 2.0 4.0 v ih v il 3.0 2.0 3.5 4.0 4.5 6820 g03 5.0 5.5 3.5 3.0 2.5 only spi pins high low supply voltage (v) 2.5 0 supply current (a) 0.5 1.0 1.5 2.0 3.0 3.0 3.5 4.0 4.5 6820 g04 5.0 5.5 2.5 slave (mstr = 0) master (mstr = 1) temperature (c) ?50 supply current (a) 3.0 25 75 6820 g05 2.0 ?25 0 50 100 125 1.0 0 2.5 1.5 0.5 v dd = 5v slave (mstr = 0) master (mstr = 1) output resistance vs supply voltage (v oh /v ol ) supply voltage (v) 1.5 output resistance () 40 60 5.5 6820 g19 20 0 2.5 3.5 4.5 100 80 output sourcing 2ma current output sinking 3.3ma current
ltc 6820 6 6820f typical p er f or m ance c harac t eris t ics driver current gain vs amplitude driver current gain vs ibias current (i b ) driver current gain vs supply voltage driver current gain vs temperature driver common mode voltage vs temperature driver common mode voltage vs pulse amplitude ibias voltage vs temperature ibias voltage load regulation ibias voltage vs supply voltage v dd = v dds , unless otherwise noted. ibias current (ma) 0 ibias pin voltage (v) 2.000 2.005 0.8 6820 g08 1.995 1.990 0.2 0.4 0.6 1.0 2.010 v dd = 3v supply voltage (v) 2.5 1.990 ibias pin voltage (v) 1.995 2.000 2.005 2.010 3 3.5 4 4.5 6820 g09 5 5.5 i b = 0.1ma i b = 1ma pulse amplitude v a (v) 0 17 current gain a ib (ma/ma) 18 19 20 21 22 23 0.5 1.0 1.5 6820 g10 2.0 v dd = 3v i b = 1ma v dd = 5v i b = 1ma v dd = 5v i b = 0.1ma v dd = 3v i b = 0.1ma v a(max) = 1.6v for v dd > 3.3v v a(max) = 1.3v for v dd = 3v ibias current (ma) 0 current gain (ma/ma) 19.5 20.0 20.5 0.6 1.0 v a = 1v 6820 g11 19.0 18.5 18.0 0.2 0.4 0.8 21.0 21.5 22.0 v dd = 5v v dd = 3v supply voltage (v) 2.5 current gain (ma/ma) 20.0 6820 g12 19.0 18.0 3.5 4.5 3 4 5 21.0 22.0 19.5 18.5 20.5 21.5 v a = 1v i b = 0.1ma i b = 1ma 5.5 temperature (c) ?50 current gain (ma/ma) 21.5 25 6820 g13 20.0 19.0 ?25 0 50 18.5 18.0 22.0 21.0 20.5 19.5 75 100 125 i b = 0.1ma, v dd = 5v v a = 1v i b = 0.1ma, v dd = 3v i b = 1ma, v dd = 5v i b = 1ma, v dd = 3v temperature (c) ?50 ?25 0 driver common mode (v) 2 5 0 50 75 6820 g14 1 4 3 25 100 125 i b = 0.1ma, v dd = 5v i b = 0.1ma, v dd = 3v i b = 1ma, v dd = 5v i b = 1ma, v dd = 3v v a = 1v pulse amplitude (v) 0 driver common mode (v) 3.0 4.0 5.0 6820 g15 2.0 2.5 3.5 4.5 1.5 1.0 0.5 1.0 1.5 2.0 i b = 0.1ma, v dd = 5v i b = 0.1ma, v dd = 3v i b = 1ma, v dd = 5v i b = 1ma, v dd = 3v temperature (c) ?50 ?25 1.96 ibias pin voltage (v) 1.98 2.04 0 50 75 6820 g07 2.02 2.00 25 100 125 v dd = 3v 3 parts i b = 1ma i b = 0.1ma
ltc 6820 7 6820f typical p er f or m ance c harac t eris t ics v dd = v dds , unless otherwise noted. wake-up pulse amplitude vs dwell time comparator threshold gain vs icmp voltage comparator threshold gain vs common mode comparator threshold gain vs temperature spi signal and isospi pulses, mstr = 1 spi signal and isospi pulses, mstr = 0 start-up time cs 5v/div sck 5v/div mosi 5v/div mis0 5v/div ip-im 2v/div 1.2s/div 6820 g21 v dd = 5v v dds = 3.3v pha = 1 pol = 1 cs 5v/div sck 5v/div mosi 5v/div mis0 5v/div ip-im 2v/div 1.2s/div 6820 g22 v dd = 5v v dds = 5v pha = 0 pol = 0 cs 5v/div ibias 2v/div ip-im 1v/div 1s/div 6820 g06 v dds = 5v mstr = 1 r bias = 2k 3.6s icmp voltage (v) 0 comparator threshold gain (v/v) 0.52 0.50 0.54 0.56 0.6 1.0 1.6 6820 g16 0.48 0.46 0.44 0.2 0.4 0.8 1.2 1.4 3 parts v dd = 3v v dd = 5v common mode voltage (v) 1.5 2.0 comparator threshld gain (v/v) 2.5 3.5 4.0 6820 g17 3.0 4.5 5.55.0 v icmp = 1v v dd = 3v v icmp = 0.2v v dd = 5v v icmp = 0.2v v dd = 3v v icmp = 1v v dd = 5v 0.52 0.50 0.54 0.56 0.48 0.46 0.44 temperature (c) ?50 ?25 comparator threshld gain (v/v) 0 50 75 6820 g18 25 100 125 v dd = 3v 3 parts v icmp = 1v v icmp = 0.2v 0.52 0.50 0.54 0.56 0.48 0.46 0.44 wake-up dwell time, t dwell (ns) 0 wake-up pulse amplitude, v wake (mv) 150 200 600 6820 g20 100 50 150 300 450 300 250 guaranteed wake-up region v dd = 3v
ltc 6820 8 6820f p in func t ions (qfn/msop) mosi (pin 1/pin 2): spi master out/slave in data. if connected on the master side of a spi interface (mstr pin high), this pin receives the data signal output from the master spi controller. if connected on the slave side of the interface ( mstr pin low), this pin drives the data signal input to the slave spi device. the output is open drain, so an external pull-up resistor to v dds is required. miso (pin 2/pin 3): spi master in/slave out data. if con- nected on the master side of a spi interface ( mstr pin high), this pin drives the data signal input to the master spi controller. if connected on the slave side of the interface (mstr pin low), this pin receives the data signal output from the slave spi device. the output is open drain, so an external pull-up resistor to v dds is required. sck (pin 3/pin 4): spi clock input/output. if connected on the master side of the interface ( mstr pin high), this pin receives the clock signal from the master spi controller. this input should not be pulled above v dds . if connected on the slave side of the inter face ( mstr pin low), this pin outputs the clock signal to the slave device. the output driver is push-pull; no external pull-up resistor is needed. cs (pin 4/pin 5): spi chip select input/output. if con- nected on the master side of the interface ( mstr pin high), this pin receives the chip select signal from the master spi controller. this input should not be pulled above v dds . if connected on the slave side of the interface ( mstr pin low), this pin outputs the chip select signal to the slave device. the output driver is push-pull; no external pull-up resistor is needed. v dds (pin 5/pin 6): spi input/output power supply input. the output drivers for the sck and cs pins use the v dds input as their positive power supply. the input threshold voltages of sck, cs , mosi, miso and en are determined by v dds . may be tied to v dd or to a supply above or below v dd to level shift the spi i/o. if separate from v dd , con- nect a bypass capacitor of at least 0.01 f directly between v dds and gnd. pol (pin 6/pin 7): spi clock polarity input. tie to v dd or gnd. see operation section for details. pha (pin 7/pin 8): spi clock phase input. tie to v dd or gnd. see operation section for details. v dd (pin 8/pin 9): device power supply input. connect a bypass capacitor of at least 0.01 f directly between v dd and gnd. im (pin 9/pin 10): isolated interface minus input/output. ip (pin 10/pin 11): isolated interface plus input/output. mstr (pin 11/pin 12): serial interface master/slave selector input. tie this pin to v dd if the device is on the master side of the isolated interface. tie this pin to gnd if the device is on the slave side of the isolated interface. slow (pin 12/pin 13): slow interface selection input. for clock frequencies at or below 200 khz, or if slave devices cannot meet timing requirements, this pin should be tied to v dd . for clock frequencies above 200 khz, this pin should be tied to gnd. gnd (pin 13/pin 14): device ground. icmp (pin 14/pin 15): isolated interface comparator voltage threshold set. tie this pin to the resistor divider between ibias and gnd to set the voltage threshold of the interface receiver comparators. the comparator thresholds are set to 1/2 the voltage on the icmp pin. ibias (pin 15/ pin 16): isolated interface current bias. tie ibias to gnd through a resistor divider to set the interface output current level. when the device is enabled, this pin is approximately 2 v. when transmitting pulses, the sink current on each of the ip and im pins is set to 20 times the current sourced from pin ibias to gnd. limit the capacitance on the ibias pin to less than 50pf to maintain the stability of the feedback circuit regulating the ibias voltage. en (pin 16/pin 1): device enable input. if high, this pin forces the ltc6820 to stay enabled, overriding the internal idle mode function. if low, the ltc6820 will go into idle mode after the cs pin has been high for 5.7ms (when mstr pin is high) or after no signal on the ip/im pins for 5.7ms ( when mstr pin is low). the ltc6820 will wake-up less than 8 s after cs falls ( mstr high) or after a signal is detected on ip/im (mstr low). exposed pad (pin 17, qfn package only): exposed pad may be left open or connected to device gnd.
ltc 6820 9 6820f b lock diagra m o pera t ion + ? i drv ip ibias i b icmp im r m 6820 bd r pu r b1 r b2 tx = ?1 cs tx ? 20 ? i b tx = +1 rx = +1 rx = ?1 ? + threshold 0.5x 35k 35k v dd ready r bias = r b1 + r b2 open when idle + 167mv v icmp 3 idle timeout wake detect cs en 2v sck gnd miso mosi en v dds v dds v dd pha pol slow mstr v dd -powered configuration inputs v dds -powered spi pin translation timing pulse qualification logic v dd 0.1f (to miso if mstr = 1) (to mosi if mstr = 0) the ltc6820 creates a bidirectional isolated serial port interface ( isospi) over a single twisted pair of wires, with increased safety and noise immunity over a nonisolated interface. using transformers, the ltc6820 translates standard spi signals ( cs , sck, mosi and miso) into pulses that can be sent back and forth on twisted-pair cables. a typical system uses two ltc6820 devices. the first is paired with a microcontroller or other spi master. its ip and im transmitter/receiver pins are connected across an isolation barrier to a second ltc6820 that reproduces the spi signals for use by one or more slave devices. the transmitter is a current-regulated differential driver. the voltage amplitude is determined by the drive current and the equivalent resistive load ( cable characteristic impedance and termination resistor, r m ). the receiver consists of a window comparator with a differential voltage threshold, v tcmp . when v ip C v im is greater than +v tcmp , the comparator detects a logic +1. when v ip C v im is less than Cv tcmp , the comparator detects a logic C1. a logic 0 ( null) indicates v ip C v im is between the positive and negative thresholds. the comparator outputs are sent to pulse timers (filters) that discriminate between short and long pulses. selecting bias resistors the adjustable signal amplitude allows the system to trade power consumption for communication robustness, and the adjustable comparator threshold allows the system to account for signal losses.
ltc 6820 10 6820f o pera t ion figure 1. typical system using tw o ltc6820 devices r m ip mstr im ibias icmp 6820 f01 mosi miso sck cs sdi sdo sck cs ltc6820 slave r m r b1 r b2 r b1 r b2 ip mstr im ibias icmp mosi miso sck cs sdo sdi sck cs ltc6820 twisted-pair cable with characteristic impedance r m isolation barrier master the transmitter drive current and comparator voltage threshold are set by a resistor divider (r bias = r b1 + r b2 ) between the ibias pin and gnd, with the divided voltage tied to the icmp pin. when the ltc6820 is enabled (not idle), i bias is held at 2 v, causing a current, i b , to flow out of the ibias pin. the ip and im pin drive currents are 20 ? i b . the comparator threshold is half the voltage on the icmp pin (v icmp ). as an example, if divider resistor r b1 is 1.21 k and resistor r b2 is 787 (so that r bias = 2k), then: i b = 2v r b1 + r b2 = 1ma i drv = i ip = i im = 20 ? i b = 20ma v icmp = 2v ? r b2 r b1 + r b2 = i b ? r b2 = 788mv v tcmp = 0.5 ? v icmp = 394mv in this example, the pulse drive current i drv will be 20ma, and the receiver comparators will detect pulses with ip-im amplitudes greater than 394mv. if the isolation barrier uses 1:1 transformers connected by a twisted pair and terminated with 100 resistors on each end, then the transmitted differential signal amplitude () will be: v a = i drv ? r m 2 = 1v (this result ignores transformer and cable losses, which will reduce the amplitude). isospi pulse detail the isospi transmitter can generate three voltage levels: +v a , 0 v, and Cv a . to eliminate the dc signal component and enhance reliability, isospi pulses are defined as symmetric pulse pairs. a +1 pulse pair is defined as a +v a pulse followed by a Cv a pulse. a C1 pulse pair is Cv a followed by +v a . the duration of each pulse is defined as t 1/2pw . ( the total isospi pulse duration is 2 ? t 1/2pw ). the ltc6820 allows for two different t 1/2pw values so that four types of pulses can be transmitted, as listed in table 1. table 1. isospi pulse types pulse type first level second level ending level long +1 +v a (150ns) Cv a (150ns) 0v long C1 Cv a (150ns) +v a (150ns) 0v short +1 +v a (50ns) Cv a (50ns) 0v short C1 Cv a (50ns) +v a (50ns) 0v long pulses are used to transmit cs changes. short pulses transmit data ( mosi or miso). an ltc6820 detects four types of communication events from the spi master: cs falling, cs rising, sck latching mosi = 0, and sck latch- ing mosi = 1. it converts each event into one of the four pulse types, as shown in table 2. table 2. master communication events spi master event transmitted pulse cs rising long +1 cs falling long C1 sck latching edge, mosi = 1 short +1 sck latching edge, mosi = 0 short C1
ltc 6820 11 6820f o pera t ion on the other side of the isolation barrier ( i.e., the other end of the cable) another ltc6820 is configured to interface with a spi slave. it receives the transmitted pulses and reconstructs the spi signals on its output port, as shown in table 3. in addition, the slave device may transmit a return data pulse to the master to set the state of miso. see isospi interaction and timing for additional details. table 3. slave spi port output received pulse spi port action return pulse long +1 drive cs high none long C1 drive cs low short C1 pulse if miso = 0 (no return pulse if miso = 1) short +1 1. set mosi = 1 2. pulse sck short C1 1. set mosi = 0 2. pulse sck a slave ltc6820 never transmits long (cs ) pulses. fur- thermore, a slave will only transmit a short C1 pulse (when miso = 0), never a +1 pulse. this allows for multiple slave devices on a single cable without risk of collisions (see multidrop section). isospi pulse specifications figure 2 details the timing specifications for the +1 and C1 isospi pulses. the same timing specifications apply to either version of these symmetric pulses. in the electrical v a +1 pulse ?1 pulse ?v a mosi, miso or cs v tcmp t 1/2pw t 1/2pw ?v tcmp v ip ? v im v a ?v a mosi, miso or cs v tcmp ?v tcmp v ip ? v im t 1/2pw t 1/2pw t inv t inv t del t del 6820 f02 characteristics table, these specifications are further separated into cs (long) and data (short) parameters. a valid pulse must meet the minimum spec for t 1/2pw and the maximum spec for t inv . in other words, the half-pulse width must be long enough to pass through the appropriate pulse timer, but short enough for the inversion to begin within the valid window of time. the response observed at mosi, miso or cs will occur after delay t del from the pulse inversion. setting clock phase and polarity (pha and pol) spi devices often use one clock edge to latch data and the other edge to shift data. this avoids timing problems associated with clock skew. there is no standard to specify whether the shift or latch occurs first. there is also no requirement for data to be latched on a rising or falling clock edge, although latching on the rising edge is most common. the ltc6820 supports all four spi operating modes, as configured by the pha and pol pins. table 4. spi modes mode pol pha description 0 0 0 sck idles low, latches on rising (1st) edge 1 0 1 sck idles low, latches on falling (2nd) edge 2 1 0 sck idles high, latches on falling (1st) edge 3 1 1 sck idles high, latches on rising (2 nd) edge figure 2. isospi differential pulse detail
ltc 6820 12 6820f o pera t ion if pol = 0, sck idles low. data is latched on the rising (first) clock edge if pha = 0 and on the falling (second) clock edge if pha = 1. if pol =1, sck idles high. data is latched on the falling (first) clock edge if pha = 0 and on the rising (second) clock edge if pha = 1. the two most common configurations are mode 0 (pha ?= 0 and pol = 0) and mode 3 (pha = 1 and pol = 1) because these modes latch data on a rising clock edge. isospi interaction and timing the timing diagrams in figures 3 and 4 show how an iso- spi in master mode ( connected to a spi master) interacts with an isospi in slave mode ( connected to a spi slave). figure?3 details operation with pha = 0 (and shows sck signals for pol = 0 or 1). figure 4 provides the timing diagram for pha = 1. although not shown, it is acceptable to use different spi modes ( pha and pol settings) on the master and slave devices. a master spi device initiates communication by lowering cs. the ltc6820 converts this transition into a long C1 pulse on its ip/im pins. the pulse traverses the isolation barrier ( with an associated cable delay) and arrives at the ip/im pins of the slave ltc6820. once validated, the long C1 pulse is converted back into a falling cs transition, this time supplied to the slave spi device. if slave pha = 1, sck will also leave the idle state at this time. before the master spi device supplies the first latching clock edge ( usually a rising edge, but see table 4 for exceptions), the slave ltc6820 must transmit the initial slave data bit s n , which it determines by sampling the state of miso after a suitable delay. if miso = 0, the slave will transmit a short C1 pulse to the master. the master ltc6820 will receive and decode the pulse and set the master miso = 0 ( matching the slave). however, if the slave miso=1, the slave does not transmit a pulse. the master will interpret this null response as a ?1 and set the master miso = 1. this makes it possible to connect multiple slave ltc6820s to a single cable with no conflicting signals (see multidrop section). after the falling cs sequence, every latching clock edge on the master converts the state of the mosi pin into an isospi data pulse (m n , m nC1 , m 0 ) while simultaneously latching the slaves data bit. as the slave ltc6820 receives each data bit it will set the slave mosi pin to the proper state and then generate an sck pulse before returning the slaves miso data ( either as a short C1 pulse, or as a null). at the end of communication, the final data bit sent by the slave ( either as a pulse or null) will be ignored by the master controller . ( the slave ltc6820 must return a data bit since it cannot predict when communications will cease.) the master spi device can then raise cs , which is transmitted to the slave in the form of a long +1 pulse. the process ends with the slave ltc6820 transitioning cs high, and returning sck to the idle state if pha = 1. rise time mosi and miso outputs have open-drain drivers. the rise time t rise for the data output is determined by the pull-up resistance and load capacitance. r pu must be small enough to provide adequate setup and hold times. slow mode when configured for slave operation, the ltc6820 provides two operating modes to ensure compatibility with a wide range of spi timing scenarios. these modes are referred to as fast and slow mode, and are set using the slow pin. when configured for master operation, the slow pin setting has no effect on the ltc6820 operation. in this case, it is recommended to tie the slow pin to gnd. in fast mode ( slow pin tied to gnd), the ltc6820 can operate at clock rates up to 1 mhz ( t clk = 1s ). however , some spi slave devices can t respond quickly enough to support this data rate. fast mode requires a slave to operate with setup and response times of 100 ns, as well as 100ns clock widths. in addition, allowances must be made for the rc rise time of mosi and miso s open- drain outputs. in slow mode ( slow pin tied to v + ), the timing requirement are relaxed at the expense of maximum data rate. as indi- cated in the electrical characteristics, the clock pulses and required setup and response times are increased to 0.9s minimum. accordingly, the minimum t clk ( controlled by the master) must be limited to 5s . the slow pin setting has no effect on the master ltc6820 ( with mstr = 1).
ltc 6820 13 6820f o pera t ion sck (pol = 0) iso iso miso mosi sck (pol = 1) sck (pol = 0) t 7 t 4 t 1 cs cs sck (pol = 1) mosi miso 500 0 1000 1500 2000 2500 time (ns) 3000 sample sample 3500 4000 4500 5000 6820 f03 t clk t 6 t 3 t 5 t 2 t 8 t 11 t 10 t 9 t del(d) t rise t rise t 10 t 16 t 14 t 13 t 18 t del(cs) sample t rtn t del(cs) csb = 0 m n m n-1 m 0 csb = 1 s n s n-1 s n-2 ignored slave does not transmit +1 t 12 t del(d) figure 3. transceiver timing diagram (pha = 0)
ltc 6820 14 6820f o pera t ion figure 4. transceiver timing diagram (pha = 1) t 7 cs sck (pol = 1) t clk t 4 t 3 t 6 t 5 t 1 t 8 t 9 t del(d) t del(cs) t 10 t 11 t 10 t 2 t 16 t 15 t del(cs) t 13 t 14 t 17 t 18 sample sample 500 1000 1500 2000 2500 time (ns) 3000 3500 4000 4500 5000 0 sck (pol = 0) mosi miso iso iso cs sck (pol = 1) sck (pol = 0) mosi miso csb = 0 m n m n-1 m o csb = 1 s n s n-1 s n-2 ignored 6820 f04 t rise t 12 t del(d) slave does not transmit +1 sample t rtn t rise
ltc 6820 15 6820f o pera t ion figure 6 demonstrates slow mode, as compared to fast mode in figure 5. figure 5. fast mode (slow = 0) figure 6. slow mode (slow = 1) ip-im 2v/div sck 5v/div mosi 5v/div miso 5v/div 200ns/div 6820 f05 v dd = 5v v dds = 5v ip-im 2v/div sck 5v/div mosi 5v/div miso 5v/div 1s/div 6820 f06 v dd = 5v v dds = 5v ip and im pulse driver the ip and im pins transmit and receive the isospi pulses. the transmitter uses a current-regulated driver ( see fig- ure?7) to establish the pulse amplitude, as determined by the ibias pin current, i b , and the load resistance. the sink- ing current source is regulated to 20 x the bias current i b . the sourcing current source operates in a current-starved (resistive) manner to maintain the sourcing pins voltage near v dd , as shown in figures 8 and 9. the common mode voltage ( while driving) is dependent on bias current and output amplitude. the output driver will regulate the common mode and peak swing of ip and im to the proper levels, allowing for a broad range of output amplitude with fairly flat gain, as shown in figure 10. + ? r m 35k open when idle + 167mv v dd v dd 35k 6820 f07 pos neg 20 ? i b pos neg v ip ? v im ip v icmp 3 im figure 7. pulse driver v ip or v im (v) 0 0 source/sink current (ma) 5 10 15 20 25 0.5 1 1.5 2 6820 f08 2.5 3 sourcing output 1v amplitude sinking output v dd = 3v i b = 1ma figure 8. drive source/sink vs output voltage pulse amplitude (v) 0 0 output voltage (v) 0.5 1.0 1.5 2.0 3.0 v cm 0.5 1 1.5 2 6820 f09 2.5 3 2.5 sourcing output sinking output v dd = 3v i b = 1ma figure 9. output voltages and common mode vs amplitude
ltc 6820 16 6820f o pera t ion figure 10. a ib current gain vs amplitude pulse amplitude (v) 0 0 current gain (ma/ma) 5 10 15 20 25 0.5 1 1.5 2 6820 f10 2.5 3 v dd = 3v i s = 1ma this type of driver does not require a center-tapped transformer, but such a transformer may improve noise immunity, especially if it has a common mode choke. see the applications information section for additional details. receiver common mode bias when not transmitting, the output driver maintains ip and im near v dd with a pair of 35k (r in ) resistors to a voltage of v dd C v icmp /3 C 167 mv. this weak bias net- work holds the outputs near their desired operating point without significantly loading the cable, which allows a large number of ltc6820s to be paralleled without affecting signal amplitude. figure 11 shows the differential and single-ended ip and im signals while transmitting and receiving data. the driver forces the common mode voltage it needs while transmitting, then it returns to the bias level with a time constant of r in ? c load /2, where c load is the sum of the capacitance at the ip and im pins. when the ltc6820 is in low power idle mode, the bias voltage is disconnected from the 35 k resistors, resulting in a 70k differential load. state diagram during periods of no communication, a low current idle (or shutdown) state is available to reduce power. in the idle state the ltc6820 shuts down most of the circuitry. a slave device uses a low current comparator to monitor for activity, so it has larger idle current. figure 11. transmitting and receiving data figure 12. state diagram time (ns) 0 ?1.5 voltage (v) ?1.0 0 0.5 1.0 400 800 1000 3.0 ip im ip-im 6820 f11 ?0.5 200 600 1.5 2.0 2.5 transmit short +1 receive short ?1 v dd = 3v i b = 1ma idle ready wake-up signal (t ready ) idle timeout (t idle ) no activity on isospi port transmit/receive 6820 f12 active in the ready state all circuitry is enabled and ready to transmit or receive, but is not actively transmitting on ip and im. supply current increases when actively communicating, so this condition is referred to as the active state. supply current table 5 provides equations for estimating i dd in each state. the results are for average supply current ( as opposed to peak currents), and make the assumption that a slave is returning an equal number of 0 s and 1s (significant because the slave doesnt generate +1 data pulses, so the average driver current is smaller).
ltc 6820 17 6820f o pera t ion table 5. i dd equations state mstr estimated i dd idle 0 (slave) 2a 1 (master) 1a ready 0 or 1 1.7ma + 3 ? i b active 0 (slave) 2ma + 3 + 20 ? 100ns ? 0.5 t clk ? ? ? ? ? ? ? i b 1 (master) 2ma + 3 + 20 ? 100ns t clk ? ? ? ? ? ? ? i b idle mode and wake-up detection to conserve power, an ltc6820 in slave mode ( mstr?=?0) will enter an idle state after 5.7ms (t idle ) of inactivity on the ip/im pins. in this condition i dd is reduced to less than 6 a and the spi pins are idled (cs = 1, mosi = 1 and sck = pol). the ltc6820 will continue monitoring the ip and im pins using a low power ac-coupled detector. it will wake up when it sees a differential signal of 240 mv or greater that persists for 240 ns or longer. in practice, a long (cs) isospi pulse is sufficient to wake the device up. once the comparator generates the wake-up signal it can take up to 8s (t ready ) for bias circuits to stabilize. figure 14 details the sequence of waking up a slave ltc6820 (placing it in the ready state), using it to communicate, then allowing it to return to the low power idle state. a ltc6820 in master mode (mstr = 1) doesnt use the wake-up detection comparator. a falling edge on cs will enable the isospi port within t ready , and the ltc6820 will transmit a long (cs ) pulse as it leaves the idle state. (the polarity of the pulse matches the cs state at the end of t ready ). the master ltc6820 will remain in the ready/active state as long as cs = 0. if cs transitions high and en ?=?0 it will enter the idle state, but not until t idle expires. this prevents the device from shutting down between data packets. in either master or slave mode the idle feature may be disabled by driving en high. this forces the device to remain ready at all times. figure 15 demonstrates a simple procedure for waking a master (mstr = 1) ltc6820 and its connected slave (mstr = 0). a negative edge on cs causes the master to drive ibias to 2 v and, after a short delay, transmit a long +1 pulse. (if cs remains low throughout t ready , the ltc6820 would first generate a C1 pulse, then the +1 pulse when cs returns high). the long pulse serves as a wake-up signal for the slave device, which responds by driving its ibias pin to 2 v and entering the ready state. |ip ac ?im ac | > 240mv ip ac im ac wake-up ip 240mv im en cs 240ns 240ns delay (filter) slave master t ready t idle idle timer ready (ibias = 2v) 6820 f13 figure 13. wake-up detection and idle timer figure 14. slave ltc6820 wake-up/idle timing figure 15. master and slave wake-up/idle sequence rejects common mode noise ip im ip-im ready t dwell t ready t idle 6820 f14 ok to communicate slave cs slave ibias ip-im master ibias master cs t dwell allow >2 ? t ready to wake master and slave t ready 6820 f15 t idle t idle t ready
ltc 6820 18 6820f ip r m ltc6820 mstr mosi miso sck cs im master sdo sdi sck cs 1 1 1 2 2 3 3 2 3 ip mstr mosi miso sck cs im slave 1 ltc6820 sdi sdo sck cs ip mstr mosi miso sck cs im slave 2 ltc6820 sdi sdo sck cs r m ip mstr mosi miso sck cs im slave 3 6820 f16 ltc6820 sdi sdo sck cs figure 16. multidropping multiple slaves on a single cable o pera t ion multidrop multiple slaves can be connected to a single master by con- necting them in parallel ( multidrop configuration) along one cable. as shown in figure?16, the cable should be terminated only at the beginning ( master) and the end. in between, the additional ltc6820 s and their associated slave devices will be connected to stubs on the cable. these stubs should be kept short, with as little capacitance as possible, to avoid degrading the termination along the cable. the multidrop scheme is only possible if the spi slaves have certain characteristics: n the spi slaves must be addressable, because they will all see the same cs signal ( as decoded by each slave ltc6820). n when not addressed, the slave sdo must remain high. when a slave is not addressed, its ltc6820 will not trans- mit data pulses as long as miso ( the spi devices sdo) remains high. this eliminates the possibility for collisions, as only the addressed slave device will ever be returning data to the master.
ltc 6820 19 6820f a pplica t ions i n f or m a t ion isospi setup the ltc6820 allows each application to be optimized for power consumption or for noise immunity. the power and noise immunity of an isospi system is determined by the programmed i b current. the i b current can range from 0.1 ma to 1 ma. a low i b reduces the isospi power consumption in the ready and active states, while a high i b increases the amplitude of the differential signal voltage v a across the matching termination resistor, r m . i b is programmed by the sum of the r b1 and r b2 resis- tors connected between the i bias pin and gnd. for most applications setting i b to 0.5 ma is a good compromise between power consumption and noise immunity. using this i b setting with a 1:1 transformer and r m = 120, r b1 should be set to 2.8 k and r b2 set to 1.2 k. in a typical cat 5 twisted pair these settings will allow for communication up to 50m. for applications that require cables longer than 50 m it is recommended to increase the amplitude v a by increasing i b to 1 ma. this compensates for the increased insertion loss in the cable and maintains high noise immunity. so when using cables over 50 m and , again, using a trans- former with a 1:1 turns ratio and r m = 120, r b1 would be 1.4k and r b2 would be 600. other i b settings can be used to reduce power consumption or increase the noise immunity as required by the applica- tion. in these cases when setting v icmp and choosing r b1 and r b2 resistor values the following rules should be used: for cables 50 meters or less: i b = 0.5ma v a = (20 ? i b ) ? (r m /2) v tcmp = 1/2 ? v a v icmp = 2 ? v tcmp r b2 = v icmp /i b r b1 = 2v i b ? ? ? ? ? ? ?r b2 for cables over 50 meters: i b = 1ma v a = (20 ? i b ) ? (r m /2) v tcmp = 1/4 ? v a v icmp = 2 ? v tcmp r b2 = v icmp /i b r b1 = 2v i b ? ? ? ? ? ? ?r b2 the maximum data rate of an isospi link is determined by the length of the cable used. for cables 10 meters or less the maximum 1 mhz spi clock frequency is possible. as the length of the cable increases the maximum possible spi clock rate decreases. this is a result of the increased propagation delays through the cable creating possible timing violations. cable delay affects three timing specifications, t clk , t 6 , and t 7 . in the electrical characteristics table, each is derated by 100ns to allow for 50 ns of cable delay. for longer cables, the minimum timing parameters may be calculated as shown below: t clk , t 6 , and t 7 > 0.9s + 2 ? t cable pull-up resistance considerations the data output ( mosi if mstr = 0, miso if mstr = 1) requires a pull-up resistor, r pu . the rise time t rise is determined by r pu and the capacitance on the pin. r pu must be small enough to provide adequate setup and hold times. for a slave device, the time constant must be less than t 12 and t 14 . in fast mode, 50ns is recommended. r pu < 50ns/c load larger pull-up resistances, up to 5 k, can be used in slow mode.
ltc 6820 20 6820f a pplica t ions i n f or m a t ion transformer selection guide as shown in figure 1, a transformer or a pair of transform- ers are used to isolate the ip and im signals between the two ltc6820s. the isospi signals have programmable pulse amplitudes up to 1.6 v, and pulse widths of 50ns and 150ns. to meet these requirements, choose a trans- former having a magnetizing inductance ranging from 50h to 350 h, and a 1:1 or 2:1 turns ratio. minimizing transformer insertion loss will reduce required transmit power; generally an insertion loss of less than C1.5 db is recommended. for optimal common mode noise rejection, choose a center- tapped transformer or a transformer with an integrated common mode choke. the center tap can be tied to a 27pf or smaller capacitor ( larger will restrict the drivers ability to set the common mode voltage). if the transformer has both a center tap and common mode choke on the primary side, a larger capacitor may be used. table 7 shows a recommended list of transformers for use with the ltc6820 . 10/100 basetx ethernet transformers are inexpensive and work very well in this application. ethernet transformers often include a common mode choke, which will improve common mode rejection as compared to other transformers. table 6. typical r b1 and r b2 values max cable length turns ratio termination resistance i b v a v tcmp v icmp r b2 r b1 idrv ready current 100m 1 :1 120 1ma 1.2v 0.3v 0.6v 604 1.4k 20ma 4.7ma 50m 1 :1 120 0.5ma 0.6v 0.3v 0.6v 1.21k 2.8k 10ma 3.2ma 100m 1 :1 75 1ma 0.75v 0.19v 0.38v 374 1.62k 20ma 4.7ma 50m 1 :1 75 0.5ma 0.375v 0.19v 0.38v 750 3.24k 10ma 3.2ma table 7. recommended transformers manufacturer part number isolation voltage turns ratio center tap cm choke pca epf8119se 1500v rms 1:1 yes yes halo tg110-ae050n5lf 1500v rms 1:1 yes yes pulse pe-68386nl 1500v dc 1:1 no no murata 78613/3c 1000v rms 1:1 yes no murata 78604/3c 1000v rms 2:1 no no pulse hx1188nl 1500v rms 1:1 yes yes epcos b82804a0354a110 1500v dc 1:1 no no ip 480 ltc6820 2:1 1:2 mstr mosi miso sck cs im c sdo sdi sck cs 480 ip mstr mosi miso sck cs im ltc2452 ltc6820 2:1 transformers sdo sck cs ip 120 ltc6820 mstr mosi miso sck cs im c sdo sdi sck cs 120 6820 f17 ip mstr mosi miso sck cs im ltc6802 ltc6820 single-transformer isolation sdi sdo sck cs figure 17. alternative isolation barriers
ltc 6820 21 6820f a pplica t ions i n f or m a t ion capacitive isolation barrier in some applications, where the environment is relatively noise free and only galvanic isolation is required, capaci- tors can be used in place of transformers as the isolation barrier. with capacitive coupling, the twisted pair cable is driven by a voltage and is subject to signal loss with cable length. this low cost isolated solution can be suit- able for short distance interconnections (1 meter or less), such as between adjacent circuit boards or across a large pcb. the capacitors will provide galvanic isolation, but no common mode rejection. this option uses the drivers in a different way, by using pull up resistors to maintain the common mode near v dd , only the sinking drive current has any effect. figure 18 shows an example application circuit using a capacitive isolation barrier capable of driv- ing 1 meter of cable. manufacturer part number capacitance voltage rating murata gcm188r 72a 104ka64 100nf 100v emc when using the ltc6820, for the best electromagnetic compatibility ( emc) performance it is recommended to use a transformer with a center tap and a common mode choke as shown in figure 19. the center tap of the trans- former should be bypassed with a 27 pf capacitor. the center tap capacitor will help attenuate common mode signals. large center tap capacitors should be avoided as they will prevent the isospi transmitters common mode voltage from settling. to improve common mode current rejection a common mode choke should also be placed in series with the ip and im lines of the ltc6820. the common mode choke will both increase emi immunity and reduce emi emission. when choosing a common mode choke, the differential mode impedance should be 20 or less for signals 50mhz and below. generally common mode chokes similiar to those used in ethernet applications are recommended. table 8. recommended common mode chokes manufacturer part number differential impedance at 50mhz common mode impedance at 50mhz tdk act45b-220-2p 20 5000 ltc6820 c mstr mosi miso sck cs ltc2640 ltc6820 sdi ip 100nf capacitive isolation im mstr mosi miso sck cs ip im sck cs 100nf 6820 f18 sdo sdi sck cs figure 18. capacitive isolation barrier 120 ip im ltc6820 6820 f19 27pf figure 19. connection of transformer and common mode choke
ltc 6820 22 6820f a pplica t ions i n f or m a t ion figure 20. example layout layout of the isospi signal lines also plays a significant role in maximizing the immunity of a circuit. the following layout guidelines should be followed: 1. the transformer should be placed as close to the isospi cable connector as possible. the distance should be kept less than 2 cm. the ltc6820 should be placed at least 1 cm to 2 cm away from the transformer to help isolate the ic from the magnetic coupling fields. 2. on the top layer, no ground plane should be placed under the magnetic, the isospi connector, or in between the transformer and the connector. 3. the ip and im traces should be isolated from surround- ing circuits. no traces should cross the ip and im lines, unless separated by a ground plane within the printed circuit board. the isospi drive currents are programmable and allow for a tradeoff between power consumption and noise immunity. the noise immunity of the ltc6820 has been evaluated using a bulk current injection ( bci) test. the bci test injects current into the twisted-pair lines at set levels over a frequency range of 1 mhz to 400 mhz. with the minimum i b current , 0.1 ma, the isospi serial link has been shown to pass a 40 ma bci test with no bit errors. a 40 ma bci test level is sufficient for most industrial ap- plications. automotive applications tend to have a higher bci requirement so the recommended i b is set to 1 ma, the maximum power level. the isospi system has been shown to pass a 200 ma bci test with no transmitted bit errors. the 200ma test level is typical for automotive testing. software layer the isospi physical layer has high immunity to emi and is not particularly susceptible to bit errors induced by noise, but for best results in a high noise environment it is recommended to implement a software layer that uses an error detection code like a cyclic redundancy check or check sum. error detection codes will allow software detection of any bit error and will notify the system to retry the last erroneous serial communication. 1.5cm ip im 1cm connector 6820 f20
ltc 6820 23 6820f typical a pplica t ions 15 hx1188nl hx1188nl 120 1.21k 2.8k 100nf 2 1 3 2 1 3 14 16 15 14 16 100nf ibias icmp gnd slow mstr ip im en cs sck miso mosi pha v dds pol v dd 1f 3v 100nf + ? to sensor sck miso in + in ? cs 6820 ta02 3.6v ltc6820 + lt6656-3 v cc v ref ltc2452 2.8k 1.21k 5v ltc6820 i q shutdown = 3.7a 120 2k ibias icmp gnd slow v dd ip im pol mstr pha en miso mosi sck cs v dds 5v remote sensor monitor with micropower shutdown 100 meter remote dac control 15 hx1188nl hx1188nl 120 604 1.4k 100nf 2 1 3 2 1 3 14 16 15 14 16 100nf ibias icmp gnd slow mstr ip im en cs sck miso pha v dds mosi pol v dd 1f 3v 100nf v out sck sdi cs 6820 ta03 3.6v ltc6820 + lt6656-3 v cc gnd v ref ltc2640 1.4k 604 5v ltc6820 120 2k ibias icmp gnd slow v dd ip im pol mstr pha en miso mosi sck cs v dds 3v out 2k
ltc 6820 24 6820f 806 1.21k ipa ibias ima icmp vm 6820 ta05 ltc6804-2 120 v reg isomd a3 a2 a1 a0 v reg isomd a3 a2 a1 a0 806 1.21k ipa ibias ima icmp vm ltc6804-2 1 2 0 806 1.21k ipa ibias ima icmp vm ltc6804-2 v reg isomd a3 a2 a1 a0 1 2 0 100nf 100nf 806 1.21k 5v ltc6820 120 2k ibias icmp gnd slow v dd ip im pol mstr pha en miso mosi sck cs v dds 5v interfacing to addressable stack of ltc6804-2 multicell battery monitors typical a pplica t ions
ltc 6820 25 6820f typical a pplica t ions 120 2k 100 806 1.21k ibias icmp gnd slow mstr ltc6820 gnd3 gnd3 ltc6803-2 v stack3 v reg czt3055 mosi miso sck cs a3 a2 a1 a0 2k 100 806 1.21k 806 1.21k v dd2 v dd2 v dd1 v dd1 ibias icmp gnd slow mstr en mosi miso sck cs ltc6820 ltc6803-2 gnd2 gnd2 gnd1 gnd1 gnd1 gnd2 gnd3 v stack2 v reg czt3055 mosi miso sck cs a3 a2 a1 a0 2k 100 ibias icmp gnd slow mstr en mosi miso sck cs ltc6820 ltc6803-2 v stack1 v reg czt3055 6820 ta04 mosi miso sck cs a3 a2 a1 a0 v dd3 v dd3 100nf 100nf 806 1.21k 5v ltc6820 120 2k ibias icmp gnd slow v dd ip im pol mstr pha en miso mosi sck cs v dds 5v en mosi miso sck cs v dds pol pha v dds pol pha v dds pol pha ip im v dd ip im v dd ip im v dd 2k 2k 2k battery monitoring system using a multidrop isospi link
ltc 6820 26 6820f p ackage descrip t ion please refer to http://www .linear.com/designtools/packaging/ for the most recent package drawings. 3.00 0.10 (4 sides) recommended solder pad pitch and dimensions 1.65 0.05 (4 sides) note: 1. drawing conforms to jedec package outline mo-220 variation (weed-4) 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package pin 1 top mark (note 6) 0.40 0.10 bottom view?exposed pad 1.65 0.10 (4-sides) 0.75 0.05 r = 0.115 typ 0.25 0.05 1 pin 1 notch r = 0.20 typ or 0.25 45 chamfer 15 16 2 0.50 bsc 0.200 ref 2.10 0.05 3.50 0.05 0.70 0.05 0.00 ? 0.05 (ud16 var a) qfn 1207 rev a 0.25 0.05 0.50 bsc package outline ud package 16-lead plastic qfn (3mm 3mm) (reference ltc dwg # 05-08-1700 rev a) exposed pad variation aa
ltc 6820 27 6820f information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. p ackage descrip t ion please refer to http://www .linear.com/designtools/packaging/ for the most recent package drawings. msop (ms16) 1107 rev ? 0.53 0.152 (.021 .006) seating plane 0.18 (.007) 1.10 (.043) max 0.17 ?0.27 (.007 ? .011) typ 0.86 (.034) ref 0.50 (.0197) bsc 16151413121110 1 2 3 4 5 6 7 8 9 note: 1. dimensions in millimeter/(inch) 2. drawing not to scale 3. dimension does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.152mm (.006") per side 4. dimension does not include interlead flash or protrusions. interlead flash or protrusions shall not exceed 0.152mm (.006") per side 5. lead coplanarity (bottom of leads after forming) shall be 0.102mm (.004") max 0.254 (.010) 0 ? 6 typ detail ?a? detail ?a? gauge plane 5.23 (.206) min 3.20 ? 3.45 (.126 ? .136) 0.889 0.127 (.035 .005) recommended solder pad layout 0.305 0.038 (.0120 .0015) typ 0.50 (.0197) bsc 4.039 0.102 (.159 .004) (note 3) 0.1016 0.0508 (.004 .002) 3.00 0.102 (.118 .004) (note 4) 0.280 0.076 (.011 .003) ref 4.90 0.152 (.193 .006) ms package 16-lead plastic msop (reference ltc dwg # 05-08-1669 rev ?)
ltc 6820 28 6820f linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com linear technology corporation 2012 lt 1112 ? printed in usa typical a pplica t ion r ela t e d p ar t s part number description comments ltc6803-2/ ltc6803-4 multicell battery stack monitor with an individually addressable spi interface functionality equivalent to LTC6803-1/ltc6803-3, allows for parallel communication battery stack topologies LTC6803-1/ ltc6803-3 multicell battery stack monitor with daisy-chained spi interface functionality equivalent to ltc6803-2/ltc6803-4, allows for multiple devices to be daisy chained ltc6903 1khz to 68mhz programmable silicon oscillator with spi interface frequency resolution of 0.01%. no external components required. operates on 2.7v to 5.5v. ltc6804-1/ ltc6804-2 multicell battery stack monitor with built-in isospi interface includes isospi interfaces for communication with master ltc6820 and to other ltc6804 devices 806 1.21k ipa ibias ima icmp vm 6820 ta06 ltc6804-1 120 120 120 v reg isomd 806 1.21k ipa ibias ima icmp vm gnd3 gnd2 ipb imb ipb imb ltc6804-1 120 120 v reg isomd 806 1.21k ipa ibias ima icmp vm gnd4 ipb imb ltc6804-1 v reg isomd 100nf 100nf 806 1.21k 5v ltc6820 120 2k ibias icmp gnd slow v dd ip im pol mstr pha en miso mosi sck cs v dds 5v interfacing to daisy-chained stack of ltc6804-1 multicell battery monitors

▲Up To Search▲

Price & Availability of LTC6803-1

	To Download LTC6803-1 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .